Embodiments of the present invention relate generally to semiconductor devices, and more particularly to the formation of vias between conductive lines in neighboring metallization layers of multi-layer integrated circuits.
In the evolution of integrated circuits in semiconductor technology, there has been a trend towards device scaling. Scaling or reducing the size increases circuit performance, primarily by increasing circuit speed, and also increases the functional complexity of the integrated circuits. The number of devices per chip has increased throughout the years. When integrated circuits contained only a small number of devices per chip, the devices could be easily interconnected in a single level. However, the need to accommodate more devices and increased circuit speed has led to the use of multi-level or multi-layer interconnects.
In a multilevel interconnection system, the area needed by the interconnect lines is shared among two or more levels, which increases the active device fractional area, resulting in increased functional chip density. Implementing a multilevel interconnect process to a fabrication scheme increases the complexity of the manufacturing process. Typically, the active devices (e.g., the transistors, diodes, capacitors and other components) are manufactured in the lower layers of wafer processing, often referred to as the Front End Of the Line (FEOL). After the active devices are processed in the FEOL, the multilevel interconnects are usually formed in the processing timeframe often referred to as the Back End Of the Line (BEOL).
As semiconductor devices continue to shrink, various aspects of multilevel interconnect processes are being challenged. The propagation delay of integrated circuits becomes limited by the large RC time delay of interconnection lines when minimum features size is decreased below about 1 xcexcm, for example. Therefore, the industry is tending towards the use of different materials and processes to improve multilevel interconnect implementations.
In the past, interconnect lines were typically made of aluminum. Now there is a trend towards the use of copper for interconnect lines because it is more conductive than aluminum. For many years, the insulating material used to isolate conductive lines from one another was silicon dioxide. Silicon dioxide has a dielectric constant (k) of approximately 4.0 or greater, where the dielectric constant value k is based on a scale where 1.0 represents the dielectric constant of a vacuum. However, now there is a move in the industry being made to the use of low-k dielectric materials (e.g., having a dielectric constant k of 3.6 or less) for the insulating material. The change in both the conductive material and insulating material used in multilevel interconnect schemes is proving challenging and requires a change in processing techniques.
Copper is a desirable conductive line material because it has a higher conductivity than aluminum. However, the RC (resistance/capacitance) time delay of copper conductive lines can be problematic, so low-k dielectric materials are used to reduce the capacitive coupling and reduce the RC time delay between interconnect lines. Some low-k insulating materials being used include organic spin-on materials, which must be heated to remove the liquid, or solvent. Often these low-k insulating materials have a high coefficient of thermal expansion (CTE) compared to metals such as copper. For example, some low-k dielectric materials have a CTE of in the order of 70 p.p.m./degrees C., compared to copper, which has a CTE of approximately 11 p.p.m./degrees C.
Semiconductor wafers are frequently temperature-cycled during fabrication due to the nature of the manufacturing process. When a device comprises a plurality of layers of metallization and dielectric materials, the solvent-removing heating step for the low-dielectric constant material layers must be repeated numerous times (e.g., each layer must be cured), which can be problematic. The mismatch of thermal expansion coefficients of metal conductive lines and low-k dielectric insulating layers results in the low-k dielectric insulating layer expanding more than the copper conductive lines. This CTE mismatch causes thermo-mechanical stress, leading to increased resistances, via delaminations, and electrical intermittencies and opens, particularly where vias contact underlying conductive lines, resulting in reduced yields.
Embodiments of the present invention achieve technical advantages as a via for connecting to an underlying conductive line and a method of forming the same that provides strength, robustness and stabile electrical resistance to metal interconnect layers of a multi-layer semiconductor device. The via is intentionally offset from an underlying conductive line. A portion of the insulating material proximate the top edge of the conductive line is removed, so that the via contacts a portion of the side of the conductive line, at the top edge. This increases the surface area so that there is a larger amount of surface area for the via to make contact with the conductive line, increasing the strength of the bond. In one embodiment, the conductive line includes an outwardly extending hook region, such that when the via is formed, a locking region is formed in the via proximate the conductive line hook region, further strengthening the structure.
In accordance with a preferred embodiment of the present invention, a method of manufacturing a semiconductor device includes providing a workpiece, disposing a first insulating layer over the workpiece, and patterning the first insulating layer with a conductive line pattern. The conductive line pattern is filled with conductive material to form at least one conductive line within the first insulating layer. The conductive line includes a top surface and at least one sidewall. A second insulating layer is disposed over the first insulating layer and the at least one conductive line. A portion of the second insulating layer is removed to expose at least a portion of the top surface of the conductive line. A portion of the first insulating layer is removed to expose at least a top portion of the at least one sidewall of the conductive line, wherein removing a portion of the second insulating layer and removing a portion of the first insulating layer comprise forming a via opening. The via opening is filled with conductive material to form a via, wherein the via makes contact with at least a portion of the top surface of the conductive line and at least a top portion of the at least one sidewall of the conductive line.
In accordance with another preferred embodiment of the present invention, a method of forming a via of a semiconductor device includes providing a workpiece, disposing a first insulating layer over the workpiece, and forming a hard mask over the first insulating layer. The hard mask and the first insulating layer are patterned, wherein patterned portions of the hard mask and the first insulating layer comprise sidewalls. A first conductive liner is formed over at least the sidewalls of the patterned hard mask and first insulating layer, and a first conductive material is formed over the first conductive liner, wherein a portion of the first conductive liner and a portion of the first conductive material comprise at least one conductive line. The conductive line includes a top surface and at least one sidewall, wherein the conductive line at least one sidewall comprises an outwardly extending hook region. A cap layer is formed over the first insulating layer and the first conductive liner, and a second insulating layer is disposed over the cap layer. A portion of the second insulating layer and a portion of the cap layer are removed to expose at least a portion of the top surface of the conductive line, and a portion of at least the hard mask is removed to expose at least a top portion of the at least one sidewall of the conductive line, wherein removing a portion of at least the hard mask and removing a portion of the first insulating layer comprise forming a via opening. A second conductive liner is formed over at least the second insulating layer, and a second conductive material is formed over the second conductive liner, wherein a portion of the second conductive liner and a portion of the second conductive material within the via opening form a via. The via makes contact with at least a portion of the top surface of the conductive line and at least a top portion of the at least one sidewall of the conductive line, and a portion of the via second conductive material is disposed beneath the conductive line hook region to form a locking region within the via proximate the conductive line hook region.
In accordance with yet another preferred embodiment of the present invention, a semiconductor device includes a workpiece, a first insulating layer disposed over the workpiece, and at least one conductive line formed within the first insulating layer, the conductive line having a top surface and at least one sidewall. The conductive line at least one sidewall includes an outwardly extending hook region. A second insulating layer is disposed over the conductive line and the first insulating layer, and at least one via is formed within the second insulating layer over the conductive line, wherein the via makes contact with at least a portion of the top surface of the conductive line and at least a top portion of the at least one sidewall of the conductive line.
Another preferred embodiment of the invention is a semiconductor device including a workpiece, a first insulating layer formed over the workpiece, and a hard mask formed over the first insulating layer. Portions of the first insulating layer and portions of the first hard mask comprise sidewalls. At least one conductive line is formed within the first insulating layer and the hard mask. The conductive line includes a liner disposed over at least the sidewalls of portions of the first insulating layer and portions of the hard mask. The conductive line also includes a fill material comprising copper disposed over the liner. The conductive line includes a top surface and at least one sidewall. A cap layer is disposed over at least the hard mask, and a second insulating layer comprised of a low-k dielectric material is formed over the cap layer. A via is formed extending through the second insulating layer and the cap layer to abut at least a portion of the top surface of the conductive line, wherein the via extends through at least the hard mask to abut at least a top portion of the at least one sidewall of the conductive line.
Advantages of embodiments of the present invention include preventing delamination, breakage and opens from occurring between vias and underlying conductive lines, during thermal expansion in multi-level interconnect structures, due to the various materials having different thermal expansion coefficients. Intentionally offsetting the via from an underlying conductive line results in increased surface area for the conductive line and via connection, improving the strength and robustness of the interconnect structure, especially during temperature cycling. The locking offset vias of the present invention provide a sturdy, robust, structure that can withstand the thermal cycling during the many times a wafer is exposed to high temperatures in order to cure low-dielectric constant insulating materials, and also during other processing steps. The invention results in improved yields and lowered electrical resistance value of vertical interconnect connections within the wafer.
The foregoing has outlined rather broadly the features and technical advantages of embodiments of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of embodiments of the invention will be described hereinafter which form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the conception and specific embodiments disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims.